The present invention relates to a phase-locked loop (hereinafter referred to PLL) for a transmission system included in a portable terminal for converting an intermediate frequency (IF) signal into a radio frequency (RF) signal mainly in the mobile communication and the portable terminal for the radio communication using the PLL.
A PLL system using a local signal frequency fLO to convert an input signal frequency fIF into an output signal frequency fLQ-fIF is described in Chapter 10.3 of “PHASELOCK TECHNIQUES” (ISBN 0-471-04294-3) published by John Wiley & Sons and is shown in FIG. 10. In FIG. 10, a phase comparator 18 compares a phase of an input signal frequency fIF with a phase of a reference signal frequency fREF and produces a signal proportional to a phase difference between the two input signals. The output signal of the phase comparator 18 is supplied to a low pass filter (LPF) 19 in which unnecessary harmonic components and noise are removed from the output signal and an output signal of the low pass filter is supplied to a VCO 20. An output frequency fRF of the VCO 20 is supplied through a coupler 21 to a mixer 22 to be mixed with a local signal frequency fLO. An output frequency fREF of the mixer 22 is given by fREF=fLO−fRF. Since the output frequency fREF of the mixer 22 is equal to the frequency fIF when the PLL is in the lock state, the input signal frequency fIF is converted into the output frequency fRF=fLQ−fIF of the VCO 20.
As other examples of the PLL system for the frequency conversion, U.K. Patent No. GB 2 261 345 and U.S. Pat. No. 5,313,173 may be referred to. These references also use the same method as the fundamental principle of the PLL circuit.
In the above-described circuit, the output signal of the phase comparator is directly supplied to the low pass filter. Accordingly, in order to obtain a shorter settling time, it is necessary to broaden the frequency bandwidth of the PLL. On the other hand, however, when the frequency bandwidth is broadened, there is a problem that output noise is increased. Further, the circuit described in Chapter 10.3 of “PHASELOCK TECHNIQUES” (ISBN 0-471-04294-3) published by John Wiley & Sons is not considered to be used in a portable terminal.
FIG. 11 illustrates an example of a circuit configuration for shortening the settling time when a voltage output type phase comparator is used. The PLL circuit includes the voltage output type phase comparator 23, a voltage controlled oscillator (VCO) 24, a coupler 25, a mixer 26, a reset switch 27, a power supply 28 for use in shortening of a settling time and a low pass filter 29. Usually, in the PLL circuit, the low pass filter, the VCO and the coupler are mounted externally to the PLL circuit. In this example, since the reset switch 27 and the power supply 28 are connected to the low pass filter 29, the reset switch 27 and the power supply 28 are also mounted externally to the PLL circuit.
While the PLL operation is performed, the reset switch 27 is open (off state). When the PLL circuit is in the phase-locked state, the VCO 24 produces an output signal having a fixed frequency as a center frequency. A small radio communication apparatus such as a portable telephone mostly performs transmission in the time division manner. In this operation, a transmission period in which the PLL circuit is locked to perform transmission with the fixed center frequency and a transmission stop period in which the PLL operation is canceled after the transmission period are performed repeatedly. Further, there is a communication system in which the transmission frequency is changed at a certain period. In such a case, the PLL is locked to the same or different frequency after a predetermined period from cancellation of the locked state. For this end, a voltage for resetting the PLL operation is supplied to the VCO. The reset switch 27 is provided in order to apply the reset voltage. When the reset switch 27 is closed (on state), an input potential of the VCO 24 becomes 0 volts and the output frequency becomes a minimum oscillation frequency.
The voltage output type phase comparator 23 requires an operational amplifier 272 for converting a voltage output into a current output in order to supply a current to a low pass filter 271. The operational amplifier 272 is necessarily required to adjust its operation characteristic and accordingly it is difficult to fabricate the operational amplifier into an IC chip. The negative DC voltage power supply 28 applies a negative bias voltage to an inverted input of the operational amplifier 272 to thereby shorten the settling time of the PLL. Since it is difficult to generate this negative voltage within the IC chip, the circuit of the negative voltage power supply 28 must be disposed outside the IC chip.